For some reason the IDE controller(s) was sometimes picking up stale
data during bus master DMA to the drive. Assuming that there was no bug
in the CPU it had to be the North bridge that was caching the stuff when
it shouldn't have been. I assume the problem would also apply to other
bus masters (SCSI, NIC etc).
Scanning the motherboard manual showed up a chipset setting "PCI master
read caching" which I suspect is the culprit. According to the manual
this defaults to "on" for Athlons and "off" for Durons (obviously other
BIOSes / MB might treat this setting differently). Unfortunately my BIOS
does not allow me to change this setting independently , I only have
the choice of running the machine in "normal" or "optimal" configuration
to alter this setting ("optimal" is the default).
In "normal" mode my machine is rock solid and I see no corruption,
however "normal" mode also changes a lot of other settings (AGP speed,
DRAM interleave etc). Anyone experiencing such corruption should look
for a BIOS setting which disables this "feature".
If anyone out there has a BIOS which allows them to change just this one
setting can they diff the "lspci -vvxxx" output with the setting off and
then on so we can isolate which host bridge biti(s) control this feature.
Maybe we can then add it to 'pci_quirks' and reduce the number of VIA
 the BIOS appears to let you change the option but it defaults the
option the moment you leave the "advanced settings" screen :-(
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