I think you mean C1 and C3, but I know what you mean.. :)
[C3 code snipped]
> There is no halt here... the interrupts are enabled for only
> a couple of
> instructions (one comparison and a jump) before being disabled again.
> It seems to me if the computer gets into S3 it'll effectively
> die until
> some kind of busmaster device wakes it up (DMA?).
The problem I've had in fixing this code is that it WorksForMe(TM). I cannot
reproduce the problem on my machine (an IBM T20). That's the way the code
was, so I left it (the code I changed/broke was the C2/C3 latency calcs).
Since you have a symtomatic system, if you're willing to do some testing to
either prove or disprove your theory (that entering C2/C3 interrupts enabled
helps things) I would greatly appreciate it.
Also, the next ACPI update will let you disable using this code for idle (so
we have some breathing room while we fix it) and will print some more C
state info on boot, because although you don't say, it sounds like you have
a desktop system, which usually don't support C2/C3, and so should not be
trying to enter them.
Regards -- Andy
(ACPI maintainer)
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