To me those quotes don't address the question we're asking. We know
that bus cycles _do_ occur when a TLB entry is switched from clean to
dirty, and furthermore they are locked cycles. (Don't ask me how I know
Does that mean, in jargon, the TLB does not "contain
the translation information" for a write?
The second quote: sure, if we want the TLB updated we have to flush it.
And eventually in mm/mprotect.c we do. But what before, it keeps on
using the old TLB entry? That's ok. If the entry was already dirty
then we don't mind if processor 2 continues with the old TLB entry for a
while, until we do the big TLB range flush.
In other words I don't think those two quotes address our question at
What worries more is that this is quite a subtle requirement, and the
code in mm/mprotect.c is not specific to one architecture. Do all SMP
CPUs support by Linux do the same thing on converting TLB entries from
clean to dirty, or do they have a subtle, easily missed data integrity
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