It has nothing to do with smp ;)
spl levels are actually faster, because hardware interrupt locking
routines are poorly optimized in processors.
I looked at P-6 instruction timing table and found:
PUSHF 16 upos
POPF 17 uops
CLI 9 uops
STI 17 uops
I think soft interrupt locks like this would be better (at least on i386):
cli:
movb $0, intr_lock
sti:
movb $1, intr_lock
testb $1, intr_pending
jnz somewhere_away_to_handle_defered_interrupt
save_flags:
movb intr_lock, %al
restore_flags:
movb %al, intr_lock
testb %al, intr_pending
jnz somewhere_away_to_handle_defered_interrupt
And - of course - interrupt checks intr_lock in its entry and if it is
zero, sets intr_pending and exits immediatelly.
Mikulas
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/