In the erase case though, yes there should be a flush. However
during the 1-2 seconds it takes to erase a sector, you can with
very high certainity guarantee that the direct-mapped unified 8
kB cache on the CRIS is flushed from any flash references at
all.. I mean, it's one-way as\sociative, during 1-2 seconds it
executes potentially 200 million instructions. So we haven't
really bothered to think about the problem..
For other CPU's it might be more dangerous, although I don't hold
my breath.. 1-2 seconds is a long time when talking about L1
I don't know about the CRIS (never heard of it, what is it?), but on
an Athlon when benchmarking stuff, I could still see L1 cache hits
from data that was 15 seconds old under certain work-loads (obviously
not gcc!). Does anyone know how old something may exisit in cache
before being written back to RAM?
Even though you potentially execute millions of instructions, they
are often the same ones over and over when the machine is near idle.
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