Linux Sparc V9 code optimazation

Ramil.Santamaria@tais.toshiba.com
Fri, 29 Jun 2001 10:20:29 -0700


To any Sparc guru,

This question relates to the effect of instruction alignment on a Sparc's
Prefetch/Dispatch unit.

Just how exactly does the branch prediction bits for instruction pairs in
the I-Cache utilized.

I'm trying to figure out the consequences of an odd word fetch into an
Instruction cache line with a the fourth
instruction being another branch.

Please cc me as I am currently not on the mailing list.

Ramil J.Santamaria
Toshiba America Information Systems
(949) 461-4379
(949) 206-3439 - fax
ramil.santamaria@tais.toshiba.com

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/