The aic7xxx's register space only supports 8byte accesses. The driver
only uses 8 byte accesses, but *may* touch consecutive registers with
consecutive accesses. As the manual suggests, PCI only allows you to
merge these kinds of requests IFF the memory region is marked as
prefetchable. The aic7xxx BAR register does not set the prefetchable
bit, and thus should never be placed in a prefetchable region. If the
BIOS or Linux is putting these registers into a prefetchable region, then
that is the root of the bug. If byte merging occurs regardless of the
type of region the registers are mapped into, then the byte merging
feature is broken.
>Why does the old driver boot fine with this enabled, and has the new
>driver troubles booting then?
The old driver issues a PCI read after every write to a register. Writes
can be posted. Reads cannot. This forces the transactions to be executed
individually, but also has a tremendous performance impact (perhaps as much
as 10x the cost per write transaction). There are times where a read is
required to synchronize state (e.g. ensure the chip has seen a write prior
to referring to some in-core data structures) and the new driver will issue
the extra reads only in that case.
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