> Can someone point me to the proper code/information that deals with
> how the processor knows that the memory corresponding to the ethernet
> device is no longer up-to-date? Is it somehow marked as
> non-cacheable, or is it snooped, explicitly flushed, or what?
This is extremely architecture specific. Some, like the x86, have a fully
coherent architecture, so the caches snoop the bus for invalidations. Others
(older parisc) are completely incoherent and won't invalidate the CPU cache
unless explicitly told to do so.
The code for all this is in:
asm/io.h for the basic dma_cache_* functions
asm/pci.h for the pci bus pci_dma_* functions
See Documentation/DMA-mapping.txt for a partial explanation of the
> The platform in question is a Motorola MCPN765 card, with a PPC7400
> processor, running a modified 2.2.17 kernel.
I believe (although you should take better advice from the PPC people) that
the powerpc is completely cache coherent, so any coherency problems you may be
having would be due to the hardware, not the kernel.
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to firstname.lastname@example.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/