> Could you also get an lspci -v dump of the ISA bridge and the IDE function
> please?
Bus 0, device 11, function 0:
ISA bridge: Symphony Labs W83C553 (rev 16).
Bus 0, device 11, function 1:
IDE interface: Symphony Labs SL82c105 (rev 5).
IRQ 31.
Master Capable. Latency=72. Min Gnt=2.Max Lat=40.
I/O at 0xe000000001100800 [0xe000000001100807].
I/O at 0xe000000001100000 [0xe000000001100003].
I/O at 0xe000000001100c00 [0xe000000001100c07].
I/O at 0xe000000001100400 [0xe000000001100403].
I/O at 0xe000000001101000 [0xe00000000110100f].
I/O at 0xe000000001101400 [0xe00000000110140f].
> Does the Engineering notice give PCI INTC as a pre-condition?
Yes. When bit 11 (LEGIRQ) of the IDE control/status register is set IDE
IRQs are sent to INTC and/or INTD. This is a pre-condition. The
problem is that the controller gets confused on an unfinished DMA and
erroneously waits for ack on IRQA/B.
>>The patch should apply to 2.5.13 - 2.5.16 (at least).
>>
>
> I think you mean 2.4.13 - 2.4.16 8)
No kidding. A Monday I guess :(.
-todd
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