Re: Athlon PSE/AGP Bug

Russell King (rmk@arm.linux.org.uk)
Tue, 22 Jan 2002 00:43:59 +0000

On Tue, Jan 22, 2002 at 01:37:43AM +0100, Andrea Arcangeli wrote:
> On Mon, Jan 21, 2002 at 02:19:31PM -0800, David S. Miller wrote:
> > That's not true, see the ptrace() helper code. Russell King pointed
> > this out to me last week and it's on my TODO list to fix it up.
>
> Where? :) ptrace doesn't change pagetables, no need to flush any tlb in
> ptrace.

See:

int access_process_vm(struct task_struct *tsk, unsigned long addr, void *buf, int len, int write)
{
...
flush_cache_page(vma, addr);
...
}

flush_cache_page() is passed a non-page aligned address. AFAIK that is
the only instance where the flush_{cache,tlb}_* stuff is called with
non-page aligned addresses.

-- 
Russell King (rmk@arm.linux.org.uk)                The developer of ARM Linux
             http://www.arm.linux.org.uk/personal/aboutme.html


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