Re: Athlon/AGP issue update

[David S. Miller]

   From: David Woodhouse <[e-mail]>
   Date: Wed, 23 Jan 2002 11:44:48 +0000
   
   [e-mail] said:
   >  speculative write operations always set the cache line dirty bit,
   > even if the write operations is not executed (e.g. discarded due to a
   > mispredicted jump) 
   
   How predictable is this? Dealing with non-coherent memory is perfectly
   normal - could we manage to work around this problem by flushing the caches
   when the CPU _might_ have dirtied a cache line rather than only when we know
   we've actually written to memory? Something like...
   
It isn't so simple.  You would have to catch every single store to
every page in the 4MB mapped region that happens to contain GART
mapped pages.

This isn't the way to solve this problem, trust me. :)