Re: thread_info implementation
Richard Henderson (email@example.com)
Mon, 11 Feb 2002 21:57:35 -0800
On Mon, Feb 11, 2002 at 09:32:48PM -0800, David S. Miller wrote:
> BTW, your "4 issue" comments assume the cpu can do 4 non-FPU
> instructions per cycle, most I am aware of cannot and I think ia64
> even falls into the "cannot" category. Doesn't it?
ia64 and alpha ev6 can do this easily. They both have
four integer pipelines.
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