Re: SMP P4 APIC/interrupt balancing

Maciej W. Rozycki (macro@ds2.pg.gda.pl)
Thu, 18 Apr 2002 10:23:33 +0200 (MET DST)


On Wed, 17 Apr 2002, Steffen Persvold wrote:

> Hmm, is that something ServerWorks specific because on my Plumas chipset
> the timer interrupt is balanced just fine :

It's specific to certain timer IRQ routing setups, ServerWorks being one
of them. I consider them braindamaged but that's just my opinion. We
handle them fine (modulo bugs).

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

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