> PPC also guarantees every ordering when using the 'sync' instruction, so
> that will give correctness at the price of a 1000 cycles or so. You
> refer to different rules for cached vs uncached on other implementations
> -- that is the essence of our problem. Are there different barrier
> instructions in MIPS which provide different levels of performance for
> different ordering enforcements?
>
> Dave.
No, there aren't. The implementation details can affect which
primitives need to explicitly sync, though.
For instance, the BRCM1250 makes some guarantees about visibility of
uncached writes that aren't strictly required by the architecture spec.
-Justin
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