> An example of where these primitives get us into trouble is the use of
> wmb() to order two stores which are only to system memory (where a
> lwsync would do for ppc64) and for a store to system memory followed by
> a store to I/O (many examples in drivers).
1) Does that only affect memory barriers, or both memory barriers and
example (from drivers/net/natsemi.c)
readw(ioaddr+whatever); // assumes that the register window is 0.
writew(1, ioaddr+PGSEL) selects a register window of the NIC. Are writew
and the spinlock synchonized on ppc64?
2) when you write "system memory", is that memory allocated with
kmalloc/gfp, or also memory allocated with pci_alloc_consistent()?
I've always assumed that
is ordered, i.e. the memory write happens before the writew. Is that
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