I agree for general chipsets, but my whole point was with regard to
buggy chipsets which need to be serialized on both channels.
If you're saying that even these broken chipsets are OK with having
transfers on one channel while setting up transfers on another channel,
then perhaps you are right but that's not what I believed to be the case
(can't find info to tell me either way right now).
But if that really were the case, then how could the (e.g.) cmd640
problem ever have been manifested? A spinlock is ALWAYS held while
ide_do_request is executing. Even if it weren't, only an SMP machine
could be trying to program both channels simultaneously because
interrupts are disabled too.
Neil
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