Can you point me at any sources/references that can
enlighten me on how this works? I did find some
additional information in the IA32 s/w dev guide
(particularly, vol 3-10.3.2) which reiterated your
response, but it seemed to give short shrift to the
mechanism behind it (it suggested that the magic was
in the snooping by the memory controller and cpu).
--- "David S. Miller" <email@example.com> wrote:
> From: William Chow <firstname.lastname@example.org>
> Date: Thu, 30 May 2002 13:44:06 -0700 (PDT)
> If IA32 builds use the i386 version of
> pci_alloc_consistent(), how is the memory
> provided by
> this function really write-thru (on a pentium)
> it appears to only set up the default mapping
> (PCD/PWT==0)? In contrast, pgprot_noncached() and
> pci_mmap_page_range() explicitly set these bits
> on a
> pentium (i.e. when boot_cpu_data.x86 > 3). Or am
> missing something?
> pci_mmap_page_range maps I/O memory, like frame
> buffers and
> device registers.
> pci_alloc_consistent promises only that CPU writes
> will be coherent
> with PCI device DMA activity. For Pentium this
> holds true with all
> normal ram, because once the cpu does the store
> coherent transactions
> on the system bus (from, for example, the PCI
> device) will take a hit
> on the L2 cache line of the cpu and thus the cpu
> will provide the most
> up to date copy of the data.
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