Re: PCI DMA to small buffers on cache-incoherent arch
David S. Miller (email@example.com)
Sat, 08 Jun 2002 17:53:25 -0700 (PDT)
From: Roland Dreier <firstname.lastname@example.org>
Date: 08 Jun 2002 17:40:24 -0700
Or should we leave that usage unless it is observed causing
problems (since we almost always get lucky and don't touch the rest
of the cache line near the DMA)?
I think passing in a 4 byte chunk and assuming the rest of the
cacheline is unmodified is a valid expectation the more I think
This means what MIPS is doing is wrong. For partial cacheline bits it
can't do the invalidate thing.
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