> It has nothing to do with "buggy" PCI-PCI bridges, and everything to do
> with the fact that a lot of bridges seem to extend on the official PCI
> bridge interface in various ways. In particular, it seems to be fairly
> common to have the _real_ bridging information in the chip-specific range
> (PCI config area 0x40+) instead of in the official "2 mem resources, 2 IO
> resources" place.
OK, that makes sense. (The "buggy" wasn't intended as any kind of
put-down, it was just what I had been told.)
What ends up in the official places? Zeroes, maybe?
Can we discriminate between these bridges, and bridges which use the
official places but where the firmware has closed an aperture? I
really would like the code not to assume the bridge is transparent in
the latter case.
Paul.
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