> On our NUMA P6 box, we found that the local APICs would occasionally start
> spasming with error interrupts. An APIC bus analyzer didn't show any kind of
> errors on the APIC bus. They would just weird out and all attempts to clear
> the error had no effect. We never did find a solution to that one or get an
> adequate explanation from Intel. The only kludge that worked was to turn off
> the APIC error interrupt.
>
> Naturally, the cleaned up version of the apic_state_dump patch wouldn't do
> that, or would make it an option.
Since you have the bus analyzer, how frequent (if at all) have you seen
the EOI register being written to without any bit set in the ISR?
Thanks,
Zwane
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