It'e entirely possible that a DMA engine reset could reasonably set CIV to
any of 0 (CIV = 0, offset 0), beginning of next SG segment (CIV + 1,
offset = 0), beginning of current SG segment (CIV unchanged, offset = 0).
I wasn't bothering to try and figure it out on each chip that we support,
instead I was just calling a reset to make the hardware stop everything
and get back to a sane state, then I would set the actual value to where
ever we wanted it to be. In most cases, that was either CIV + 1, offset =
0 or CIV = 0, offset = 0. However, that was really only a convenience,
not a requirement.
> But if CIV is really RO, I could add a CAP_CIV_RO define to the card_cap
> struct. Then I'd only have to set LVI appropialty to CIV... hmmm....
No, I wouldn't do this. If there are some chips now that have a read only
CIV, then no big deal. We change the DMA engine to treat all chips as
having a read only CIV and then we don't bother needing to know which ones
have which capability and we only need one DMA engine to drive all chips,
> BTW, sound is working perfectly on my machine (ICH4).
Well, that could just be luck ;-) The particular sound problem that
Andris is seeing is related to DMA start and stop operations. If you
happen to be using an artsd or esd daemon that is configured to DMA
silence when there isn't anything else going on, then DMA on your machine
would *not* be starting and stopping and you wouldn't see this problem.
That's why my standard battery of tests includes using play from the
command line without X running at all since it actually starts and stops
the DMA with each operation and does lots of drain_dac() calls.
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