> This patch implements a system that modifies the kernel code at runtime
> depending on CPU features and SMPness.
> This patch requires the is_smp() patch I posted earlier and also
> requires the new CPU selection code and the code that actually uses
> This code already exists, but needs a few adjustments so it may not
> arrive immediately.
> The code is invoked in the following ways:
> * Undefined exception handler: this is used to replace
> unsupported instructions with supported ones. Used for invlpg
> -> flushall, prefetchnta -> prefetch -> nop, *fence -> lock
> addl 0, (%esp), movntq -> movq
> * Int3 handler: this is used when a 1 byte opcode is desired.
> This is controlled by a config option so that debuggers and
> kprobe won't break. Used for lock/nop and APIC write
Why not do *everything* using int3 handler? It should simplify your code.
Hooking on 'unknown instruction' should not be really neccessary if you
replace all invlpgs (etc) with 0xcc...
> Unfortunately with this patch executing invalid code will cause the
> processor to enter an infinite exception loop rather than panic. Fixing
> this is not trivial for SMP+preempt so it's not done at the moment.
Using 0xcc for everything should fix that, right?
-- Philips Velo 1: 1"x4"x8", 300gram, 60, 12MB, 40bogomips, linux, mutt, details at http://atrey.karlin.mff.cuni.cz/~pavel/velo/index.html.
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