> which currently has two problems Ross found
>
> 1. The processors or so fast we have to enforce the 400nS delay nowdays
What about PCI write posting ? How can we enforce the 400ns delay here ?
I suspect we can't read back from the taskfile registers after writing
the command. Especially when using DMA, I think I remember Andre telling
me even tapping alt status might not be safe... So we need to issue
a read from the same bus path, but not on any taskfile register from
this channel... hrm... any idea ?
> 2. The code is racey in some situations with a shared IRQ because we
> may get an IRQ after we set the handler but before we send the command,
> or implemnted the other way the command can complete before we set the
> handler.
Yup, that's an old problem indeed.
Ben.
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