Jim> The current TSC synchronization may have an error on the order
Jim> of 1 microsecond on a quad processor system. Not a big deal
Jim> but annoying if you are trying to figure out what order things
Jim> happen based on TSC time stamps.
Jim> Since the IA64 folk already solved this problem, I did a quick
Jim> hack based on the itc sync code.
Cool. I'm glad to see the code is proving useful on other architectures.
I was hoping that would be the case.
BTW: The algorithm is documented in Section 8.5.2 of my book (see
http://www.lia64.org/book/). If there is enough interested, I'd be
willing to try to talk the publisher into releasing that section as a
PDF (or perhaps HTML).
--david
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