Dave
diff -urpN --exclude-from=/home/davej/.exclude bk-linus/arch/i386/kernel/cpu/intel.c linux-2.5/arch/i386/kernel/cpu/intel.c
--- bk-linus/arch/i386/kernel/cpu/intel.c 2003-02-25 13:10:08.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/intel.c 2003-02-25 13:07:52.000000000 -0100
@@ -8,6 +8,7 @@
#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/uaccess.h>
+#include <asm/system.h>
#include "cpu.h"
@@ -75,6 +76,36 @@ static int __init P4_disable_ht(char *s)
}
__setup("noht", P4_disable_ht);
+/*
+ * Some 'overdrive' boards, such as those from Powerleap don't have
+ * the L2 cache enabled, and the BIOS doesn't know about it, so we
+ * have this option to 'force' it on.
+ */
+static int __init P2_enable_L2(char *s)
+{
+ unsigned long cr0, lo, hi;
+
+ printk ("CPU: Enabling L2 cache.\n");
+
+ __asm__ ("cli");
+
+ cr0 = read_cr0();
+ cr0 |= 1<<30;
+ write_cr0 (cr0);
+
+ rdmsr (0x11e, lo, hi);
+ lo |= 0x40101;
+ wrmsr (0x11e, lo, hi);
+
+ cr0 &= ~(1<<30);
+ write_cr0 (cr0);
+
+ wbinvd();
+ __asm__("sti");
+ return 0;
+}
+__setup("enable-l2", P2_enable_L2);
+
#define LVL_1_INST 1
#define LVL_1_DATA 2
#define LVL_2 3
-
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