RE: [BUG] 2.5.63: ESR killed my box!

[Mallick, Asit K]

I want to correct the cumulative part:

> 
> It is the real value. Error interrupt is generated when any 
> bit is set in the real value (error bits) and does not use 
> visible ESR. However, the ESR (latch) bits are cumulative and 
> if the ESR is not cleared (using 2 writes) when we handle the 
> interrupt the read of ESR status will also contain the errors 
> for the previous error. So, the interrupt handler also should 
> use the clear and read current state as you mentioned.

The error interrupt is generated based on the real error bits and
readable ESR bits does not affect the interrupt generation (did verify
with the architects). We need the back-to-back write only to make the
readable ESR to get 0 on a read. So, the interrupt handler should be
able to use the write to ESR and read of ESR to get the current error
status.

Thanks,
Asit