Re: [patch 2.5] PCI MWI cacheline size fix
Greg KH (firstname.lastname@example.org)
Thu, 20 Mar 2003 14:26:11 -0800
On Thu, Mar 20, 2003 at 01:59:50PM +0300, Ivan Kokshaysky wrote:
> This is rather conservative variant of previous patch:
> - no changes required for drivers or architectures with HAVE_ARCH_PCI_MWI;
> - do respect BIOS settings: if the cacheline size is multiple
> of that we have expected, assume that this is on purpose;
> - assume cacheline size of 32 bytes for all x86s except K7/K8 and P4.
> Actually it's good for 386/486s as quite a few PCI devices do not support
> smaller values.
> If you all are fine with it, I can make a 2.4 counterpart.
This looks fine to me.
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