L1_CACHE_SHIFT again
Margit Schubert-While (margitsw@t-online.de)
Sun, 23 Mar 2003 12:55:16 +0100
According to the Intel docs, the cacheline for a P4 is
64 bytes. The P4 does, on read, 2 sectors of 64 bytes.
But, on write, 64 bytes.
So, is the cache line size wrong ? (7 in 2.4 and 2.5)
Margit
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