Re: NOP instruction

[Jamie Lokier]

On Tue, Dec 15, 1998 at 09:02:53AM -0500, Richard B. Johnson wrote:
> The problem is that it's a single byte instruction. If you have nicely
> aligned instructions, obtaining data on longword aligned addresses,
> fetching instructions on longword aligned addresses, the machine is
> very happy and cache-line refills are transparent. However, if you
> throw in a bye-size opcode, instruction fetches are no longer aligned
> so the machine slows down. The trick is to find an instruction sequence
> that does nothing, but maintains 4 byte alignment.

But must x86 instructions don't maintain 4 byte alignment, and the x86
architectures are reasonably happy decoding misaligned instructions.
(Ok, cache boundary effects, blah blah...)

They just don't like jumping to them.  Hence realignment for labels.

-- Jamie