Linux-kernel mailing list archive 1999-51,: Re: readX/writeX semantic and ordering

# Re: readX/writeX semantic and ordering

Jeremy Fitzhardinge (jeremy@goop.org)
Tue, 21 Dec 1999 02:47:04 -0800 (PST)

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On 20-Dec-99 Gabriel Paubert wrote:
> On Mon, 20 Dec 1999, Gerard Roudier wrote:
>> I have been reported some problem on the G3 that seems to disappear when
>> the cache is set write-through. Could a bridge misconfiguration explain
>> that ?
> Do you have any pattern about which type of G3 (uP revision, size of
> backside L2 cache, output of lspci, especially host bridge) ?

MPC750 ("Arthur") rev 2.2, 1MB backside (also happens with 512k), bridge is
MPC106 ("Grackle"), rev 4.0.

With L2 in copy-back, it appears the sym'896 mis-DMAs stuff from system memory,
and/or gets out of sync with the IO operations into PCI space. With L2 in
write-through mode, it appears to work OK, even though L1 is still copy-back
and enabled. When it fails, it fails after about .5-1 hour of heavy SCSI
activity; I've never observed a failure with L2 in write-through, but without a
clear understanding of what the failure it, I'm not convined its fixed (as
opposed to merely much less likely).

The '106 has very few configuration options which could affect snooping, and
none apply to single CPU systems (I think). The '106 always sets /GBL, which
should cause the L2 to be snooped (there is a 750 bug where the L2 could be
mis-snooped with non-GBL 60x bus cycles).

J

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