Hi Dave,
from looking at the CVS tree and the latest pre-patch it looks as if
the two are back in sync WRT the SPARC architecture. Am i correct?
Now while trying to compile the latest pre-patch i got a failure in
ide-geometry.c (Why is that compiled unconditionally into the block device
driver code in the first place i wonder, after all not all systems have
IDE interfaces/drives...). I got over that by simply copying the sparc64
version of hdregs.h and ide.h over to sparc and change were the compiler
bailed out. Now here are my questions:
1. Does ide_ioreg_t need to be a long on sparc as well or will a short do
as on the other archs?
2. In ide.h the functions inw_be() and outw_be() set ASI_PHYS_BYPASS_EC_E,
which according to asi.h is "PADDR, E-cachable, E-bit". Now the v8 MMU
apparently does not have this condition instead i used ASI_M_BYPASS on
a wild guess. Is that correct?
3. In ide.h the functions ide_insw() and ide_outsw() both finish with
"__flush_dcache_range()". That function does not exist on sparc. Is that
not possible on older SPARC chips or simply not (yet) implemented?
Simply omitting "__flush_dcache_range()" and applying step 1 and 2 gives me
a clean compile up to srmmu.c...
Yours,
Dominik Kubla
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.rutgers.edu
Please read the FAQ at http://www.tux.org/lkml/