Re: [patch-2.3.46-p2] P6 microcode update support

[H. Peter Anvin]

On Wed, 16 Feb 2000, Tigran Aivazian wrote:
> 
> Also, more importantly, Intel manual says "the update must run in the
> early stages of POST and always before L2 cache controllers are
> initialized". I ignored it and it still worked fine. However, on the bus
> to work this morning I thought "perhaps I should use some MSRs to
> disable cache and re-enable it?". I will think on this in the background
> but first rewrite it as a char driver.
> 

This stuff is really the job of the BIOS rather than the operating system.
This device should only be used if the BIOS is old/substandard.  By the
time the OS has booted, you have done way too much work already.

> Thanks for your feedback,
> 
> I suppose I need to ask Peter to grant me minor=180 of the major=10
> (misc character drivers)? And most difficult part - think of a short
> name prefix abbreviation for "Intel P6 Microcode Update Device" - IMU?
> /dev/imu

Far too short for such a hardware-specific device.  Also, minor 180 is
taken.  I suggest /dev/microcode actually.  It's quite self-explanatory,
and can be used for other CPUs with microcode updates as well.

Major 10, minor 184.

	-hpa

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