Re: [PATCH][CFT] dcache-ac6-D - dcache threading

Andi Kleen (ak@suse.de)
Mon, 5 Jun 2000 11:11:13 +0200

On Mon, Jun 05, 2000 at 10:06:55AM +0100, Jones D (ISaCS) wrote:
> > Hmm, another guess would be that CONFIG_X86_L1_CACHE_BYTES
> > does not match the CPU's real cache size.
>
> You'd guess right. They define the number of bytes per cache line.

Ok, cache line size. It was a typo. No need to be anal.

For CONFIG_I386 CONFIG_X86_L1_CACHE_BYTES is 16, which would give lots
of false sharing on pentium.

Kumon, could you check that that is not the case ?

At least for Williamette with bigger cache lines it prevents us from having
a single SMP kernel (or otherwise it requires wasting a lot of memory)

Seems the times for single binary SMP kernel are over with 2.4.

-Andi

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