Re: dcache-ac6-D - dcache threading

kumon@flab.fujitsu.co.jp
Mon, 5 Jun 2000 18:37:43 +0900

Andrey Savochkin writes:
> > near line 1520 in eepro100.c:
> > do {
> > HERE>>> status = inw(ioaddr + SCBStatus);
> > /* Acknowledge all of the current interrupt sources ASAP. */
> > /* Will change from 0xfc00 to 0xff00 when we start handling
> > FCP and ER interrupts --Dragan */
> > outw(status & 0xfc00, ioaddr + SCBStatus);
>
> Are you able to estimante the time of this inw() per call?

The result is shown below.

I put two counters in speedo_interrupt: one is just before the above
"do{" statement this counts the call-count of speedo_interupt.
another is just after the "inw" statement, for counting the "inw"
instruction.

I split counters for every CPU to eliminate overhead. Result shows
that values are not so varied among CPUs, only few percent difference
observed.
So, I show only the total statistics.

System: Xeon 450MHz x 4, 2MB cache
OS: linux-2.4.0-test1-D (viro patch)
Benchmark: mindcraft WebBench

Speedo interrupt handling frequecy:
speedo_interrupt calls 33.7K/s
"do{}" execution 71.5K/s

These values mean the do{}-loop is executed 2.16 times per function
call.

At that moment, the WebBench transaction speed may be over 3500
tran/s, but I forget to measure the exact value.

Following values are that you requested:
lock aquire 280ns/call
movzwl(inw) 1580ns/call or 750ns/loop
lock release 230ns/call

FYI: 1 CPU clock is 2.2ns@450MHz
lock aquire: if (test_and_set_bit(0, (void*)&sp->in_interrupt)) {
lock release: clear_bit(0, (void*)&sp->in_interrupt);

Huum, "movb" instruction should be applied to exit-lock, again.

Is it enough for you?

--
Computer Systems Laboratory, Fujitsu Labs.
kumon@flab.fujitsu.co.jp


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