Re: Cache coherency... and locking

[Manfred Spraul]

Keith Owens wrote:
> 
> I could not find an absolute statement of this requirement, just lots
> of mail about spinlock optimisation that assume strong write ordering.
> See http://www.uwsg.iu.edu/hypermail/linux/kernel/9911.3/0148.html
> where Linus says "Basically, everybody agrees on ordering of writes".

That thread was about the ia32 architecture: we reduced the memory
ordering of spin_unlock() - it was a full memory barrier, now it's a
simple move - spin_unlock doesn't need to be a full memory barrier,
release semantics is sufficient. And on ia32, a simple move has release
semantics

>
> It would be nice if the kernel gods made a definitive statement about
> the need or otherwise for strong write ordering.
> 

I'm interested in the ordering of atomic_xy and bit operations: I heard
that they must be full memory barriers, but at least the ia64 port only
uses a partial memory barrier.

> >Neither ia64 nor the other RISC processors guarantee strong write
> >ordering.
> 
> IA64 load.acquire and store.release are available to do strong write
> ordering, although the default option is weak order.

Correct: the spinlock/semaphore functions use these .acquire and
.release asm instructions, but a simple

	global_variable_1 = 7;
	global_variable_2 = 9;

can be seen by other cpus in any order.

--
	Manfred