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Homework                                          [ Sivu suomen kielellä]

Operating Systems II,  Spring 2006, HW 1

This will be covered in practise session during the week 12 (20.-24.3.2006)

These are normal, conventional homeworks. Problems are to be solved independently (or preferable working with a small group, with individual solutions) in advance at home and then the solutions are discussed in practice session. There will be no model solutions - make enough questions in the practice session.

1. Interrupts, I/O
   1. What happens if a device interrupt (I/O interrupt) occurs but device interrupts are disabled? How can this problem be avoided? Why would one want to disable device interrupts?
   2. What trouble would it cause, if the processor would not be able to recognize I/O interrupts? Could one build a processor like this and for what purpose?
   3. Problem 1.8 [Stal05] (Probl. 1.8 [Stal01]) ("Problem", not "Review Question"!)
       
2. Concurrency control
   1. What is the most important difference between synchronization with lock variables and synchronization with semaphores?
   2. Give an example situation where it would be advisable to synchronize with lock variables and not with semaphores.
   3. Give an example situation where it would be advisable to synchronize with semaphores and not with lock variables. 
   4. Give an example situation where one definitely should not use (i) lock variables and (ii) semafores for synchronization.
   5. Considering synchronization with lock variables, what effect would many processors with local caches have? Is this an advantage or disadvantage? Would it be better to place lock variables to a non-cacheable memory area (memory area that is not cached)? Why?
       
3. Cache and TLB
   1. Problem 1.13 [Stal05] (Probl. 2.3 [Stal01])
   2. How does the situation change, if we consider also virtual memory address translation and TLB?
      Assume that address translation is done according to the Figure 8.8 [Stal05] (Fig. 8.8 [Stal01]) before cache access. TLB hit ratio is 99% and the page table is found in main memory with 95% probability. TLB has the same speed as cache.
       
       
4. Scheduling
   1. Problem 2.3 [Stal05] (Probl. 2.4 [Stal01]) from the text book (higher level answers, no details)
   2. How do scheduling policies for optimizing real time systems differ from those for time sharing and multiprogramming systems.
      
         
5. W2K
   1. What advantages/disavantages is there with the HAL layer (Fig. 2.13 [Stal05] or Fig. 2.13 [Stal01])?
   2. Can Win32, DOS and POSIX applications simultaneously execute in W2K systems? If not, why? If yes, can the co-operate and how? Give an example where this feature could be (i) advantageous (ii) disadvantegous.
   3. MS-DOS has no threads but W2K has threads and a MS-DOS API (application program interface). Will this cause any problems? Give an example.

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Teemu Kerola 06.03.2006 16:13