From: "William Stallings" To: Subject: coa errata Date: 2. syyskuuta 2004 4:56 Errata File (August 2004) Computer Organization and Architecture, Sixth Edition William Stallings (Prentice-Hall, ISBN 0-13-035119-9) ------------------------------SYMBOLS USED------------------------------- | ti = ith line from top; bi = ith line from bottom; Fi = Figure i | | X -> Y = replace X with Y; Ti = Table i; Pi = Problem i | ------------------------------------------------------------------------- ------------------------------------------------------------------------- //////////////////////////////////AUGUST LIST//////////////////////////// ------------------------------------------------------------------------- PAGE CORRECTION 700 LHS of the generalization of De Morgan's theorem: T -> Y ------------------------------------------------------------------------- //////////////////////////////////JUNE LIST////////////////////////////// ------------------------------------------------------------------------- 20 F2.3: Delete (ALU) after Program control unit 36 T2.6d: 9.5 million transistors in Pentium III 78 F3.21, Top left: Address(2nd cycle) -> Data(2nd cycle) 82 T3.3: clock rates up to 66 MHz are supported 111 F4.8 16-Kword cache -> 16-Kline cache 114 F4.10 16-Kword cache -> 16-Kline cache 115 Add to footnote: The 15-bit set plus word portion of the main memory address is represented in the figure by a 4-digit hexadecimal number. The most significant digit in only 3 bits in length. 117 F4.12 16-Kword cache -> 16-Kline cache 153 F5.11 caption: SEC-DEC -> SEC-DED 173 b17: 15,000 rpm -> 7500 rpm 174 t8: 500 -> 2500, so the result is 20.04 seconds 212 b17: Figure 3.25 -> Figure 3.26 217 F7.11: line missing from R0 to A0 218 F7.12: DMA request and ACK lines should point in opposite direction 226 F7.18: bottom layer box is Physical Layer 228 F7.19c: delete Ack and final Isoch gap 230 b11: FCAs -> HCAs 231 t8:than temporarily -> than another destination device can receive it, a pair of queues at both ends of each link temporarily 232 F7.21: IBA -> IB (which means Infiniband) 234 Delete problems 7.3 and 7.4 248 T8.2: Multiprogramming memory use = 63% 249 F8.6a: CPU utilization of J2, J3 should be 10%, not 20% Memory utilization: J1=20% J2= 40%, J3=30%; this changes both charts 267 F7.18, box on Yes branch of Memory full: Perform page replacement 292 lower gray box: result should be 1 followed by only 7 zeros 299 F9.10: 1001 -> 1011 308 F9.18b: 1.638125 -> 1.6328125 326 P9.4a: (2n-X) -> (2^n-X) P9.4b: Figure 9.2 -> Figure 9.5 P9.8: x = 5 328 P9.28: Insert (d) 76545336; make current (d) be part (e) 369 10.14: Table 10.11 -> Table 10.10 375 F10.16 caption: Stock -> Stack 378 F10.18a: 6161 -> 6162 442 t16: Table 10.8 -> Table 10.9 502 P13.4: CMP ECX, 101 instr missing between the INC and the JNE 543 T15.1: RISC-line -> RISC-like 597 b15: 1901 -> 2001 607 T17.1: In ACC1 and ACC2, digit should always be a subscript 740 PB.11: decimal -> hexadecimal 743 last 2 paragraphs of discussion of SMPCache refers to SimpleScalar by mistake ------------------------------------------------------------------------ | A current version of this file, named Errata-COA6e-mmyy, | is available at WilliamStallings.com ------------------------------------------------------------------------