581365 Computer Organization II (19.8.2013)
| Principal Theme | Prerequisite knowledge | Approaches the learning objectives | Reaches the learning objectives | Deepens the learning objectives |
|---|---|---|---|---|
| Digital logic | Knows the concepts Boolean variable and truth value (Discrete mathematics) |
Can explain computer operation at electrical component (gates, circuits, flipflops) level. Can build a truth table to describe circuit function. Can describe basic functionality of flipflops. Can list basic gates and explain the basic idea of how circuits fgunction and describe their use in data storage. |
Can implement a given logical function with combinational circuits and optimize it with Karnaugh maps Can explain the operation of clocked flipflops< and the register implementation with flip-flops |
Can explain the Quine- McKluskey or Lugue methods to simplify combinational circuits Can explain the combinatorial circuit implementation of addition and ROM-memory circuits Can consider timing and voltage problems in implementing circuits |
| Component communication | Can explain the need for component communication and how it can be implemented (CO-I) |
Can describe the meaning and function of hierarchical component interconnects in component communication. |
Can list the differences of bus arbitration methods and describe their signal level implementation. |
Can explain the signal level operation for the latest bus and point-to-point interconnect types. |
| Memory |
Can explain the huge speed differences of various memory devices, as well the significance of them (CO-I). Can explain why cache< memory is needed (CO-I). Know the basic ideas of cache and virtual memory operations (CO-I) . |
Can explain memory reference actions when both cache and virtual memory are used. Can list and describe cache organization methods, their types and policies governing them. Can explain address translation in (multilevel) virtual memory, possibly using inverted page table. Can list the requirements and basic features for TLB operation. |
Can explain the need for and implementation of cache memory hierarchy with separate instruction and data caches. Can explain the details of set-associative cache operation. Can explain with details how TLB operates, including its replacement policies. Can explain the similarities and differences of TLB and cache. Can estimate the memory reference time considering both virtual memory and cache effects. |
Can explain differences between Rambus DRAM and normal DRAM. Can explain TLB and cache memory details for some certain CPUs. Can explain various replacement policies for virtual memory back-up store. |
| Arithmetic |
Can explain addition and multiplication algorithms with paper and pencil (high school). Can explain the IEEE floating point presentation (CO-I). |
Can explain integer basic arithmetic circuit level implementation. Can explain Booth’s algorithm. Can explain IEEE floating point presentation for very large and very small numbers. Can list and describe floating point rounding methods. |
Can explain the implementation of 2’s complement addition and subtraction. Can apply Booth’s algorithm for multiplication. Can explain the basics of IEEE floating point arithmetic implementation. |
Can explain precisely integer division implementation Can explain detailed implementation for IEEE arithmetic implementation. |
| Instruction sets |
Can explain instruction execution cycle and the differences between machine and symbolic assembly language (CO-I). Can explain different data reference methods and where data can locate (CO-I). |
Can describe and compare instruction sets based on their fundamental features Can explain machine instruction components, meaning of registers, and ways to store multi-byte data. |
Can classify instruction based on their features and processors based on their instruction sets. Can explain the structure and data reference methods for real instruction sets (e.g., Intel Pentium and ARM11). |
Can give examples of Load- Store processors. Can explain registers, data types and data reference methods for Intel Pentium and Arm 11 processors. |
| Processor structure and operation |
Can explain the basic idea of von Neumann processor architecture (CO-I) Can explain instruction fetch execute cycle operation (CO-I) |
Can explain processor general structure at register and control unit level. Can explain the basic idea of pipelining and superscalar processor and give examples of their dependency problems. Can compare RISC and CISC architectures. |
Can compute the speed advantage obtained with pipelining Can give solutions to problems caused by structural, control and data pipeline dependencies. Can explain how RISC and CISC architectures can be combined |
Can explain special registers and interrupt mechanisms in Intel Pentium and ARM11. Can explain basic ideas of combining multiple processor architectures in Intel Pentium II and Transmeta Crusoe processors. Can explain exact operation in executing multiple instructions simultaneously in IBM PowerPC and Intel IA-64 processors |
| Control |
Can explain machine language execution at micro-programmed control level. Can explain how control signals for instruction fetch-execute cycle are produced with a state automata. Can explain the basic idea of microprogrammed control. Can explain the function of control memory in micro-programmed control. |
Can explain hard-wired and microprogrammed< control. Can explain how clock cycle length is determined. Can explain the differences, advantages and disadvantages of horizontal and vertical micro-programming. Can explain the advantages and disadvantages of various ways to select next micro-program instruction. |
Can explain, how modern processor combines microprogrammed and direct control. Can explain precise implementation of some current processors. |
Printer-friendly version