And will you please stop behaving like this is not an issue?
> K6-2 or 486s I checked exhibited the worrisome behaviour you're
And I maintain that this kind of race condition can not be tickled
deterministically. There might be some piece of logic (or absence of it),
that can show that your finding of a thousand runs is not relevant.
> speculating about, plus it is logically consistent with the statements the
> manual does make about updating ptes; otherwise how could an smp os
Don't say this anymore, specially if you can not point me to the specs.
> perform a reliable shootdown by doing an atomic bit clear on the present
> bit of a pte?
OS clears present bit, processors can keep using their TLBs and access
the page, no problems at all. That is why after clearing the present bit,
the processor must flush all tlbs before it can assume no one is using
the page. Hardware updated access bit could also be a problem, but an
error there does not destroy data, it just leads the os to choosing the
wrong page to evict during memory pressure.
Kanoj
>
> -ben
>
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