Re: PCI power management

[Jeff Garzik]

Benjamin Herrenschmidt wrote:
> >When a device comes out of D3[hot], the equivalent of a soft reset is
> >performed. From D3[cold], PCI RST# is asserted, and the device must be
> >completely reinitialized.
> 
> Some devices (bad bad HW designers ;) just can't do it themselves. The
> Rage M3 requires the host to assert PCI RST#, and some motherboards
> provide no documented facility for that (it might be possible with Apple
> ASICs for example, it's just not documented).

Why should we support such a non-spec device?  Tell ATI to fix their
hardware, and tell users (a) not to use the hardware, or (b) use the
hardware with the knowledge that you are screwed when it comes to Power
Management.

Unless there are more cases like this, this should not factor at all
into the modifications to the PCI and PM code...

-- 
Jeff Garzik      | The difference between America and England is that
Building 1024    | the English think 100 miles is a long distance and
MandrakeSoft     | the Americans think 100 years is a long time.
                 |      (random fortune)