Re: eepro100 (PCI ID 82820) lockups/failure

[Alan Cox]

> Shouldn't a udelay(1) always take one microsecond, regardless of
> hardware optimizations?

A udelay(1) should always take 1 microsecond or a bit longer. There are some
funnies with PCI posting to beware of - notably

	writel(0x1, foo->reg);
	udelay(1);
	writel(0x0, foo->reg)

Does _not_ guarantee the two writes hit the PCI device with a 1 uS delay 
where its PCI access timing that matters you need to do

	writel(0x1, foo->reg)
	readl(foo->somethingthatdoesnothing);
	udelay(1);
	writel(0x0, foo->reg)