PCI power management problem

[Alan Cox]

Having read the PCI power management spec it appears that at least part of
the 'something weird happend to me on the way to D0' problems are caused by
us failing to enforce the delays the spec requires.

It states that accessing the io/mm spaces during the transition times
is undefined..

--- linux.vanilla/drivers/pci/pci.c	Mon Jul 23 22:28:24 2001
+++ linux.ac/drivers/pci/pci.c	Sat Aug 11 22:55:04 2001
@@ -290,6 +290,15 @@
 	/* enter specified state */
 	pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
 
+	/* Mandatory power management transition delays */
+	/* see PCI PM 1.1 5.6.1 table 18 */
+	if(state == 3 || dev->current_state == 3)
+	{
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		schedule_timeout(HZ/100);
+	}
+	else if(state == 2 || dev->current_state == 2)
+		udelay(200);
 	dev->current_state = state;
 
 	return 0;