According to c't 18/2001 p.36, the real power saving in halt and STPCLK
is only in effect when the CPU disconnects from the FSB. In the VIA
north bridges there is one bit (bit 7 at offset 0x52) which controls
whether the north bridge performs the disconnect protocol. For various
reasons, this is usually disabled by the BIOS:
1. Lower quality power supplies and motherboard voltage regulators may
not be able to deal with the large and fast current changes.
2. Disconnect costs 2% - 3% on common benchmarks. Incidentally, this is
also the difference between the fastest and slowest Athlon
motherboards. Disconnect doesn't sell, benchmarks do.
3. The internal clock generator of the CPU may lose sync or something on
reconnect. (erratum #11, can be worked around by software)
4. In rare cases, Athlons with non-integer frequency multipliers (e.g.
7.5) may fail to reconnect altogether. (erratum #14, work around:
don't sleep in C1 or C2 with disconnect)
Errata as quoted from the article, referring to "AMD Athlon Processor
Model 4 Revision Guide",
http://www.amd.com/products/cpg/athlon/techdocs/pdf/23614.pdf
-- Andreas E. Bombe <andreas.bombe@munich.netsurf.de> DSA key 0x04880A44 - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/