>
>
>By adding three bits of colouring you're going to cut the collision of
>about 1/8.
>
No, Shuji is right:
You have just shifted the problem, without reducing collisions.
256 kB, 4 way cache with 32 byte linesize.
cacheline == bits 15..5
offset within cacheline: bits 4..0
The colouring must depend on more than just bits 13 to 15 - if these
bits are different, then the access goes into a different line even
without colouring, there won't be a collision.
Shuij, I don't understand why you need both a shift and a modulo:
address % odd_number should generate a random distribution (i.e. all
bits affect the result), even without the shift.
--
Manfred
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