The ~800MB or so of kernel address space is exhausted with struct page
entries around 48GB of physical memory or so
SGI's original highmem patch switched page tables on entry to kernel
space, so there is code already tested that we can borrow. But I'm
not sure if it's worth it as the overhead it adds makes life really
suck: we would lose the ability to use global pages, as well as always
encounter tlb misses on the kernel<->userspace transition. PAE shows
up as a 5% performance loss on normal loads, and this would make it
worse. We're probably better off implementing PSE. Of course, making
these kinds of choices is hard without actual statistics of the
usage patterns we're targetting.
> Would be nice to have a config option like "CONFIG_PCI_36" to imply
> that all devices on a PAE system were able to access all of memory,
> globally removing the need for bounce buffering and allowing a native
> PCI setup for mapping memory addresses...
That would be neat.
-ben
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