This is the problem scenario. Suppose we are doing DMA to a buffer B
and also independently accessing a variable X which is not part of B.
Suppose that X and the beginning of B are both in cache line C.
I see what the problem is. Hmmm...
I'm trying to specify this such that knowledge of cachelines and
whatnot don't escape the arch specific code, ho hum... Looks like
that isn't possible.
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