A question about cache coherence

[Xuehua Chen]

Met a problem in my research. I run some code on a
Xeon
dual-processor machine. It seems to me that there is a
 cache coherence problem. As I am not so familiar 
to this topic, I would like to ask some experts about 
the following questions.

1. Do Xeon processors have hardware mechanisms to
maintain cache coherence?
2. Does the SMP kernel handle the cache coherence
problem
3. What should I do if both of them don't handle cache
coherence.

Thanks.

Frank Samuel

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