No, you're thinking of IBM's Power4 chip, which really does have two CPU cores 
on one chip, sharing only the L2 cache.
The P4 hyperthreading shares just about all CPU resources between the two 
threads of execution.  There are only separate registers, local APIC, and 
some other minor logic for each "CPU" to call its own.  All execution units 
are demand shared between them.  (The new "pause" opcode, rep nop, allows one 
half to yield resources to the other half.)
That's why typical job mixes only get around 20% improvement.  Even optimized 
benchmarks, which run only integer code on one side and floating point on the 
other only get around a 40% boost.  The P4 just doesn't have all that many 
execution units to go around.  Future chips will probably do better.
> Cheers,
> Dick Johnson
> Penguin : Linux version 2.4.18 on an i686 machine (797.90 BogoMips).
> The US military has given us many words, FUBAR, SNAFU, now ENRON.
> Yes, top management were graduates of West Point and Annapolis.
-- 
James Cleverdon
IBM xSeries Linux Solutions
{jamesclv(Unix, preferred), cleverdj(Notes)} at us dot ibm dot com
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