Quoting section 6.8.1.3 of the PCI 2.2 spec (talking about message
control in PCI config space):
This register provides system software control over MSI. After reset,
MSI is disabled (bit 0 is cleared) and the function requests servicing
via its INTx# pin (if supported). System sofware can enable MSI by
setting bit 0 of this register. System software is permitted to
modify the Message Control register's read/write bits and fields.
A device driver is not permitted to modify the Message Control
register's read/write bits and fields.
> AFAICS, this is a per-driver decision, and needs to be done at the
> driver level, in the tg3 driver source.
The last sentence in the quote above indicates that it is not intended
(by the PCI spec) to be a per-driver decision, but rather a system
decision. The messages used are also a per-bus system resource and how
an MSI goes from the PCI bus to the rest of the system (i.e. the CPU(s))
is implementation dependent.
/jeff
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