Re: [Bug 350] New: i386 context switch very slow compared to 2.4 due to wrmsr (performance)

[Ph. Marek]

Hi Linus,

which compiler optimization should I use for this test?

-O3 shows other values:
* the empty overhead is 4 cycles shorter
* but store overhead goes from 3 to 48 cycles!

Please see below.

Regards,

Phil

gcc -O3 linus_i_d_cache.c -o linus_i_d_cache
./linus_i_d_cache

empty overhead=73 cycles
load overhead=10 cycles
I$ load overhead=10 cycles
I$ load overhead=10 cycles
I$ store overhead=48 cycles

gcc -g -Wall linus_i_d_cache.c -o linus_i_d_cache
./linus_i_d_cache

empty overhead=77 cycles
load overhead=12 cycles
I$ load overhead=12 cycles
I$ load overhead=12 cycles
I$ store overhead=3 cycles

cat /proc/cpuinfo

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 3
model name      : Pentium II (Klamath)
stepping        : 3
cpu MHz         : 265.916
cache size      : 512 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov mmx
bogomips        : 530.84